ECE 363 Logic & Computer Design

The course builds on the Digital Systems class and provides an in-depth analysis of digital design and computer architecture. Core topics include Finite State Machine (FSM) controllers and pipeline design using Hardware Description Language (HDL). Students will: understand and design sequential circuits and perform timing analysis; understand and design FSM controllers and next state decoders; understand and design pipelined processors and cache memories; design of an onboard 32x32 register file; work in a group setting to come up with innovative ideas to design and implement an FSM, a controller and a cache memory. Prerequisite: ECE 263; Corequisite: ECE 361

Credits

3

Lab Hours

0

Lecture Hours

3

Prerequisite

ECE 263

Corequisite

ECE 361